Many solutions have been proposed to improve the performance of MOSFETs with high power-handling capability (MOSFETs capable of sustaining high voltages ranging from 3 V to about 100 V and driving large currents ranging from 100 mA to about 1 A). However, the main problem is the risk of depressing other electrical characteristics of the device such as, for example, a low internal resistance, which are as important as the capability of handling high power. Furthermore, transistors for high voltage applications have to satisfy the existing demand for compact circuits, that continually steers the microelectronics industry into submicron regions and thin-oxide circuits.
One solution to high voltage tolerance for submicron dimensions has been the development of DMOSFETs. A DMOSFET is an enhancement-mode MOS transistor having a good punch-through control, which is reached by the provision of a double diffusion of dopants through the source diffusion window. In detail, two successive diffusions of dopants of opposite type (P and N) are performed through the source diffusion window in a lightly doped substrate. A portion of the first diffusion underlies a gate oxide layer and acts as a body region, within which the channel zone for the transistor conduction current forms. The second diffusion behaves as a source region and the exploited dopants are of the same type as the dopants diffused to form the drain region.
The main limitations for high voltage transistors are due to the electrical tolerances of the gate oxide layer overlapping the channel region. The high electric field at the interface between the semiconductor and the gate oxide layer makes the transistor particularly sensitive to defects and accidental, but inevitable, contaminations of the oxide layer during manufacturing.
The application of a voltage to the gate terminal causes the contaminants migration to the point of maximum stress, i.e. the so-called edge portion of the gate oxide layer, adjacent to the drain region, experiencing the maximum voltage drop. Such a migration exacerbates the stress condition by creating an extremely high electric field proximate to the trapped ions, which causes charge injection into the gate oxide.
For this reason, the oxide/semiconductor interface close to said edge portion (adjacent to the so-called drift region) undergoes a degradation; such a degradation is more evident for devices having relatively thin gate oxide layers, which consequently suffer from significant unreliability when operating at relatively high drain voltages.
The DMOS transistors can exploit an additional lightly doped region extending from the drain region to the gate and possibly from the source region to the gate, to introduce a voltage drop between the drain and source regions and the edge of the channel, reducing the electric field across the thin gate oxide layer. However, the electric field reduction achieved by the provision of these lightly doped regions (which cannot be made too lightly doped, not to excessively increase the MOSFET conduction resistance) may not be sufficient to avoid degradation of the gate oxide.
Solutions are known in the art allowing a further reduction of the electric field across the gate oxide, such as a differentiated gate oxide thickness, providing a thicker oxide layer close to the drain region that decreases the vertical electric field at the gate edge portion; however, this simple solution does not satisfy the request for thin oxide layers.
U.S. Pat. No. 5,430,316 discloses a DMOS transistor having a further region formed under the edge portion of the gate oxide adjacent to the drain region and doped with dopants of the same type as the body region dopants. This further region forces the conduction current to move away from the surface of the device down towards a buried silicon layer, before being collected by a sinker at the drain region.
V-shaped and U-shaped grooved MOS transistors have been proposed, such as the Schottky-barrier vertical MOS transistor described in U.S. Pat. No. 4,983,535. The dopants distribution is equivalent to that of a DMOS transistor, but a trench is etched to fully penetrate the body region, and the trench surfaces oxidized to form the gate oxide; the trench is filled with polysilicon, forming the gate electrode. The conduction current of the device flows parallel to walls of the etched trench and a common drain contact is provided at the bottom of the device, inducing a vertical conduction current.
The walls of trenches resulting from an etching of the wafer inevitably present a relatively low crystallographic quality and the defects of the crystalline surface of the etched trench induce a carrier mobility degradation.
In the art, trenches in high voltage MOS transistors have also been used for other purposes. For example, U.S. Pat. No. 6,093,588 discloses a high voltage MOS transistor in which, in order to save silicon area and reduce the specific internal resistance, drain regions are formed by implanting doping species into the silicon through apertures in the field oxide. In U.S. Pat. Nos. 5,385,852 and 6,437,399 trenches are etched perpendicular to the surface of a substrate, to establish electrical contacts for reducing the transistor size and for improving the control of parasitic transistors. U.S. Pat. No. 5,356,822 discloses complementary DMOS transistors in which trenches are etched in a silicon layer for electrically isolating N and P regions on which gates are formed.
There is a need for an insulated-gate transistor that ensures great reliability at high operation voltages, has reduced geometrical dimensions and, further, has reduced parasitic effects.